The present disclosure relates to semiconductor integrated circuit devices having flip chip structures and methods for designing the semiconductor integrated circuit devices.
In recent years, as device processing has employed finer design rules, the number of transistors constituting an LSI has been increasing. The increase in the number of elements constituting an LSI is likely to lead to an increase in chip area, and therefore, it is one of the most important challenges in terms of cost to reduce or prevent the increase in chip area. On the other hand, an LSI is typically connected to a package by wire bonding. When this mounting technique is used, the LSI has a structure in which IO cells are provided at a periphery of the chip. The use of this structure poses, for example, a problem that the chip area increases, depending on the number of the IO cells. In addition, when the wire bonding technique is used, it is necessary to bond wires with the IO cells by crimping, and the IO cells need to have a predetermined size or more to have sufficient strength not to collapse due to crimping. The crimping requires a relatively large area, and therefore, there is also a physical limitation on the reduction in the size of the IO cells. Because of these problems, the IO cells determine the chip area if the number of the IO cells on the chip is large in a microfabrication process. In this case, even if an attempt is made using an internal logic layout synthesis technique or the like so as to reduce the area, the overall chip area cannot be reduced.
Flip chip structures are used to solve the aforementioned problems. FIG. 19 shows a typical flip chip structure. As shown in FIG. 19, a plurality of pads 12 are provided on an entire surface of a chip 21, and the pads 12 are electrically connected to IO cells 11 provided at a periphery of the chip 21 via wires 13 called rewires. FIG. 20 shows the chip 21 of FIG. 19 which is joined with a package 22. As shown in FIG. 20, the chip (LSI) 21 is mounted face down on a surface of the package 22, and is electrically connected via the pads 12 to the package 22. The chip 21 is also covered with a resin 23 on the surface of the package 22. External electrodes 24 are provided on a back surface of the package 22. Thus, the use of the flip chip structure makes it unnecessary to perform wiring with respect to the IO cells, whereby the size of the IO cells can be reduced as compared to conventional structures. Moreover, it is no longer necessary to provide the IO cells themselves at a peripheral portion of the chip 21, i.e., a periphery of the LSI, and therefore, the problem with wire bonding (i.e., the IO cells determine the area of the LSI) can be solved. Note that, in the description which follows, pads provided on an entire surface of a chip by the flip chip technique is particularly referred to as area pads.
Incidentally, when the flip chip technique is used, it is necessary to take measures against the influence of stress applied from area pads provided on a surface of an LSI (chip) to elements provided in the LSI. Specifically, external stress is applied through the area pads to the LSI, and therefore, the LSI has both a portion to which the stress is applied and a portion to which the stress is not applied, depending on the arrangement of the area pads. Here, the stress applied to the LSI may cause a change in a characteristic of transistors located immediately below the area pads. Specifically, this influence causes the operating speed of the transistors in the LSI to be non-uniform. Therefore, the reliability of timing of the LSI is significantly degraded unless the influence is taken into consideration.
To solve this problem, Japanese Patent Laid-Open Publication No. 2001-024089 describes a technique of constructing an LSI by separately preparing a system LSI portion in which functional blocks for achieving functions are formed, and a wiring layer for connecting the functional blocks, and then joining the system LSI portion with the wiring layer. Japanese Patent Laid-Open Publication No. 2001-118946 describes that stress from pads can be reduced by providing at least one additional row of pads outside the perimeter of an LSI.